Light emitting diodes are widely used in consumer and commercial applications. As is well known to those having skill in the art, a light emitting diode generally includes a diode region on a microelectronic substrate. The microelectronic substrate may comprise, for example, gallium arsenide, gallium phosphide, alloys thereof, silicon carbide and/or sapphire. Continued developments in LEDs have resulted in highly efficient and mechanically robust light sources that can cover the visible spectrum and beyond. These attributes, coupled with the potentially long service life of solid state devices, may enable a variety of new display applications, and may place LEDs in a position to compete with the well entrenched incandescent lamp.
One difficulty in fabricating Group III nitride based LEDs, such as gallium nitride based LEDs, has been with the fabrication of high quality gallium nitride. Typically, gallium nitride LEDs have been fabricated on sapphire or silicon carbide substrates. Such substrates may result in mismatches between the crystal lattice of the substrate and the gallium nitride. Various techniques have been employed to overcome potential problems with the growth of gallium nitride on sapphire and/or silicon carbide. For example, aluminum nitride (AIN) may be utilized as a buffer between a silicon carbide substrate and a Group III active layer, particularly a gallium nitride active layer. Typically, however, aluminum nitride is insulating rather than conductive. Thus, structures with aluminum nitride buffer layers typically require shorting contacts that bypass the aluminum nitride buffer to electrically link the conductive silicon carbide substrate to the Group III nitride active layer.
Alternatively, conductive buffer layer materials such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), or combinations of gallium nitride and aluminum gallium nitride may allow for elimination of the shorting contacts typically utilized with AIN buffer layers. Typically, eliminating the shorting contact reduces the epitaxial layer thickness, decreases the number of fabrication steps required to produce devices, reduces the overall chip size, and/or increases the device efficiency. Accordingly, Group III nitride devices may be produced at lower cost with a higher performance. Nevertheless, although these conductive buffer materials may offer these advantages, their crystal lattice match with silicon carbide is less satisfactory than is that of aluminum nitride.
The above described difficulties in providing high quality gallium nitride may result in reduced efficiency of the device. Attempts to improve the output of Group III nitride based devices have included differing configurations of the active regions of the devices. Such attempts have, for example, included the use of single and/or double heterostructure active regions. Similarly, quantum well devices with one or more Group III nitride quantum wells have also been described.
One characteristic of gallium nitride that has typically been associated with poor quality is the presence of dislocation defects. These defects often appear as “V” shapes or pits that surround the dislocation. Historically, Cree, Inc. has attempted to close as many of these pits as possible before the formation of the active region of the device since it was believed that they degraded device performance attributes such as output power and stability. To this end, a “pit closing” layer has been used to close the pits prior to formation of the active region of the device. While prior Cree LEDs may have included some pits that extended through the active region, efforts were made to reduce the number of pits that extended through the active region. Such prior Cree LEDs included, for example, the multi-quantum well LEDs described in United States Patent Publication No. US2003/0006418A1 that published on Jan. 9, 2003 and in U.S. Pat. Nos. 6,664,560 and 6,734,003 which are commonly assigned to Cree, Inc. and the disclosures of which are incorporated herein as if set forth in their entirety.
In addition to the efforts at closing the pits that form at dislocations, U.S. Pat. Nos. 6,329,667 and 6,693,303 generally describe the isolation of active layer(s) from dislocations by forming a barrier layer in the pit that isolates the active layer(s) from the dislocation. For example, as described in the abstract of U.S. Pat. No. 6,693,303, a nitride semiconductor device is composed of Group III nitride semiconductors. The device includes an active layer, and a barrier layer made from a predetermined material and provided adjacent to the active layer. The barrier layer has a greater band-gap than that of the active layer. The device also includes a barrier portion formed of the predetermined material for surrounding a threading dislocation in the active layer.